Windows 2000 PCI IRQ Steering Across System Buses

PCI interrupt request (IRQ) steering in Microsoft Windows 2000 allows the operating system to dynamically assign and share hardware interrupts among multiple peripheral devices across interconnected system buses. By transitioning configuration authority from the system BIOS to the operating system's kernel and drivers, Windows 2000 eliminates standard hardware resource conflicts, manages multiple PCI-to-PCI bridges, and enables multiple PCI devices to operate reliably on a limited number of system IRQ lines.

The Problem of Legacy IRQ Allocation

Traditional x86 architecture limits systems to 16 standard IRQ lines (IRQs 0 through 15), many of which are permanently reserved for legacy system devices such as system timers, keyboards, and IDE controllers. The PCI specification introduced level-triggered interrupts that allow multiple devices to share an IRQ line, using four logical interrupt pins per slot: INTA#, INTB#, INTC#, and INTD#. However, older operating systems relied strictly on static BIOS routing at boot, which often led to resource collisions, unassigned devices, or failed initialization when multiple expansion cards or buses were present.

How Windows 2000 Controls IRQ Steering

Windows 2000 takes control of interrupt routing directly after the boot phase, bypassing BIOS-level assignments. It handles PCI IRQ steering primarily through the PCI bus driver (Pci.sys) in conjunction with the appropriate Hardware Abstraction Layer (HAL).

When enumerating hardware, Windows 2000 evaluates the motherboard's interrupt routing hardware—typically a chipset-integrated programmable interrupt router. The operating system programs this router to bind specific physical PCI interrupt pins to available ISA-compatible IRQs (such as IRQ 9, 10, or 11) or extended APIC interrupts.

Steering Across System Buses and Bridges

Modern motherboards often feature multiple PCI segments linked by PCI-to-PCI bridges. To distribute the interrupt load evenly across the system, PCI bridges implement a technique called "pin swizzling" (rotating pin assignments):

  • A device using INTA# on a secondary bus may map to INTB# on the primary bus.
  • A device using INTB# maps to INTC#, and so forth.

Windows 2000 tracks this topology hierarchically. As Pci.sys walks the device tree across primary, secondary, and subordinate buses, it calculates the physical routing back to the host bridge. The operating system maintains an internal map of how every slot and downstream bridge connects to the chipset's interrupt router, ensuring that downstream devices receive a valid, conflict-free system IRQ regardless of which bus segment they occupy.

ACPI vs. Legacy Routing Mechanisms

Windows 2000 supports two main methods for discovering and managing interrupt paths:

  1. ACPI (Advanced Configuration and Power Interface): On modern ACPI-compliant systems, Windows 2000 queries the ACPI namespace. It reads the PCI Routing Table (_PRT) object associated with each bus. The _PRT explicitly defines how each device slot and pin corresponds to either a hardwired interrupt or an ACPI Interrupt Link Device. The OS can then program these link devices dynamically.
  2. **\(PIR Table (Fallback for Non-ACPI Systems):** On non-ACPI systems (such as standard PC HAL installations), Windows 2000 reads the BIOS-provided `\)PIR(PCI IRQ Routing) table stored in the memory region between0xF0000and0xFFFFF. This table specifies the router's hardware identity, its register interface, and the physical link values for every PCI slot pin. Pci.sys` then directly manipulates the chipset registers to steer interrupts.

Extended Routing via APIC

When running on systems equipped with an Advanced Programmable Interrupt Controller (APIC) and an APIC-compatible HAL, Windows 2000 expands interrupt capacity beyond the traditional 16 IRQs. In APIC mode, the operating system routes PCI interrupts to dedicated I/O APIC inputs (typically lines 16 through 23 or higher). This significantly reduces the need to share IRQs among high-bandwidth devices, lowering interrupt latency and improving overall system throughput across all system buses.