MS-DOS 6.22 CPU Reset and Hardware Controllers

This article examines how MS-DOS 6.22 interfaces with core hardware system controllers during and immediately following a CPU reset. While a hardware reset initially places control exclusively in the hands of the system BIOS, MS-DOS 6.22 assumes management of essential controllers—such as the 8259 Programmable Interrupt Controller (PIC), the 8042 Keyboard Controller, and the 8237 Direct Memory Access (DMA) controller—as soon as its boot routines take over. Understanding this interaction clarifies the boundary between firmware hardware initialization and the operating system's configuration of low-level x86 architecture.

The Initial Reset State and BIOS Precedence

When a system undergoes a cold or warm reset, the CPU's instruction pointer is hardwired to jump to address FFFF:0000h (the reset vector). At this instant, MS-DOS 6.22 is not executing. The system BIOS executes the Power-On Self-Test (POST), during which it issues initialization command words (ICWs) to the master and slave 8259 PICs, tests the 8237 DMA controllers, and configures the 8254 Programmable Interval Timer (PIT).

Only after the BIOS completes these fundamental hardware assignments does it read the Master Boot Record and pass execution to the MS-DOS boot sector, which then loads IO.SYS and MSDOS.SYS.

Hardware Controller Management by IO.SYS

Once loaded, the MS-DOS 6.22 kernel (IO.SYS) relies heavily on the environment established by the BIOS, but it selectively reconfigures and directly communicates with specific hardware controllers:

  • Programmable Interrupt Controllers (Dual 8259 PICs): MS-DOS 6.22 accepts the BIOS default mapping of hardware IRQs (IRQ 0–7 mapped to INT 08h–0Fh, and IRQ 8–15 mapped to INT 70h–77h). Rather than reprogramming the PICs directly via I/O ports 20h/21h and A0h/A1h, DOS intercepts software and hardware interrupt vectors directly within the Interrupt Vector Table (IVT) in the first 1 KB of RAM (0000:0000h to 0000:03FFh). MS-DOS alters vectors such as INT 21h (DOS API), INT 23h (Ctrl+C handler), and INT 24h (Critical Error handler), while chaining into hardware interrupts like INT 08h (System Timer) and INT 09h (Keyboard).
  • The 8042 Keyboard Controller and the A20 Gate: MS-DOS 6.22 relies on HIMEM.SYS to utilize the High Memory Area (HMA), which spans the first 64 KB of extended memory beyond 1 MB. To prevent the real-mode address wrap-around at 1 MB, MS-DOS communicates with the 8042 keyboard controller (via ports 60h and 64h) or the Fast A20 logic (via Port 92h) to assert the A20 line, altering hardware addressing behavior at the system bus level.
  • DMA and Timer Controllers: For disk I/O, MS-DOS predominantly acts as a high-level driver delegating low-level operations to BIOS INT 13h routines. However, subsystems like disk cache utilities (SMARTDRV.EXE) monitor and interact with system timer ticks derived from the 8254 PIT (Port 40h) to schedule write-behind flushes and controller handshakes.

Software-Initiated CPU Reset

MS-DOS 6.22 frequently manages the reset sequence in reverse when a warm boot is triggered (such as via Ctrl+Alt+Del or specific installer commands). Instead of performing an immediate CPU power cycle, MS-DOS interacts with memory and the keyboard controller to reset the processor cleanly:

  1. Setting the Warm Boot Flag: MS-DOS writes the word 1234h to memory address 0040:0072h in the BIOS Data Area (BDA). This flag instructs the BIOS POST routines to bypass lengthy memory parity checks upon restart.
  2. Pulsing the CPU Reset Pin: To command the hardware to reset the CPU, code executing under MS-DOS transmits the output command 0FEh to the 8042 Keyboard Controller at port 64h. This command pulls the processor's active-low reset line low, triggering an immediate hardware CPU reset while maintaining register states appropriate for a warm start. On PS/2 and newer architectures, MS-DOS drivers may alternate this by asserting bit 0 of System Control Port A (port 92h).