How Mac OS 9 Communicated With the Power Manager
In Apple’s Mac OS 9, power management relied on a dedicated hardware microcontroller known as the Power Management Unit (PMU) interfacing with the operating system through low-level hardware drivers and system traps. This article details the communication mechanisms between the Power Manager chip and the Mac OS 9 system software, focusing on hardware-level register interfaces, command-response protocols, and interrupt handling via the PowerPC Nanokernel.
The Hardware Interconnect
The Power Manager chip—typically a custom microcontroller such as a 68HC05 variant or a dedicated PMU integrated into Apple's custom I/O controllers like Paddington or KeyLargo—operated independently of the main PowerPC processor. Communication between the main processor and the PMU took place across internal bus interfaces, primarily via the Versatile Interface Adapter (VIA) in older designs or memory-mapped I/O registers in PCI-based "New World" PowerPC architectures.
The OS accessed the PMU using specific control, data, and handshake registers mapped into the system's physical address space. Rather than executing direct memory access (DMA), the CPU exchanged bytes with the PMU through synchronous serial communication or direct byte-wide register reads and writes coordinated by hardware handshake lines.
The Command-Response Protocol
Interaction between Mac OS 9 and the PMU followed a strictly defined packet-based command-response protocol:
- Initiation: The system software initiated a transaction by asserting a request or handshake line and writing a command byte to the PMU data register.
- Payload Transfer: If the command required parameters (such as setting a real-time clock value, adjusting screen brightness, or scheduling a wake-up event), the OS transferred the length byte followed by the parameter bytes sequentially, waiting for the PMU to assert a transfer-acknowledge flag between bytes.
- Execution and Response: The PMU processed the command and loaded the requested data into its output buffer. The OS then read the status and return payload bytes in the same synchronized sequence.
Driver
Architecture and the _PowerDispatch Trap
At the operating system level, Mac OS 9 did not feature a modern monolithic or microkernel in the Unix sense; instead, it combined a low-level PowerPC Nanokernel with the classic Mac OS system architecture.
High-level software and system components interacted with the
subsystem through the Mac OS Power Manager API, exposed to applications
and system extensions via the A-line trap mechanism
(_PowerDispatch, trap word $A09E). When a
program or control panel requested a power-state change, the Trap
Manager routed the call to the native Power Manager system driver. This
driver was responsible for translating high-level requests into the
low-level byte sequences understood by the PMU hardware.
Interrupt Handling and Asynchronous Events
Because the PMU managed asynchronous hardware events—such as battery status transitions, AC adapter connections, lid-closure switches on PowerBooks, and power button presses—it required a method to alert the CPU immediately.
When an event occurred, the PMU pulled an interrupt line low. The CPU hardware routed this signal to the system's interrupt controller, which generated an interrupt exception handled by the PowerPC Nanokernel. The Nanokernel routed the exception to the native interrupt dispatcher, which in turn invoked the Power Manager's interrupt service routine (ISR).
The ISR queried the PMU using an "interrupt status" command to determine the event's cause. Once the status byte was retrieved and the hardware interrupt cleared, the Power Manager driver posted appropriate notification events to the classic Event Manager or initiated critical processes directly, such as dimming the display, dimming the processor speed, or transitioning the system into deep sleep.